A New VLSI Algorithm for a VLSI Implementation of MDST using Obfuscation Technique

A New VLSI Algorithm for a VLSI Implementation of MDST using Obfuscation Technique

연구 분야: Analysis

학회: 2022 International Symposium on Electronics and Telecommunications (ISETC)

In this paper we present a new VLSI algorithm for an efficient VLSI implementation of the Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithm decomposes the computation of the MDST into two modular and regular computational structures called pseudo-cycle convolution that have the same form. This can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array using interleaving. The obtained VLSI architecture has all the advantages of a pseudo-cycle convolution based systolic implementation, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology and low I/O cost. Moreover, a cost-effective application of an obfuscation technique can be achieved with low overheads.