FPGA-Implemented Reconfigurable Logic Locking Using N-Stage Delays for Obfuscation

FPGA-Implemented Reconfigurable Logic Locking Using N-Stage Delays for Obfuscation

연구 분야: Analysis

학회: 2025 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)

System security is becoming an increasingly essential feature of modern computing systems, particularly programmable hardware such as Field Programmable Gate arrays (FPGA), employed in various applications such as autonomous systems and digital networks. However, safeguarding FPGA-based devices against IP theft and reverse engineering is difficult and a big concern for the semiconductor and defense industries. Previously, various obfuscation approaches such as gate level obfuscation, camouflaging, and strong puff were employed to make a distinct key for every chip. These designs, however, are more area-intensive, consume more power, and are easier to crack the key. In this research, we propose a novel obfuscation idea that integrates a reconfigurable hardware obfuscation block into the original circuit with an additional N-stage Delay circuit to enhance overall system security and resistance to threats. The present idea relates to the increase in the security of the system against the piracy, overbuilding and from the cloning and camouflaging of the chip. The proposed technique does not have any bulky circuit, and it is easily realizable and just requires some additional modules that can easily reconfigured with a very smaller area and power overhead thereby offering performance benefits and increasing the time of sat attack iteration, making the locking system more complex and difficult to decode.