Securing Hardware Accelerator Against Reverse Engineering Attack

Securing Hardware Accelerator Against Reverse Engineering Attack

연구 분야: Analysis

학회: 2023 IEEE International Conference on Consumer Electronics (ICCE)

Hardware Accelerators (HAs) have a significant contribution to the fast and uninterrupted functioning of a System-On-Chip (SoC). HAs are mostly used as reusable Intellectual Property (IP) in the SoCs to speed up the design process. This makes HAs susceptible to several hardware attacks like IP counterfeiting, IP cloning, inserting hardware Trojan etc. Reverse Engineering (RE) the HA design is one of the primary steps while launching those attacks. Hardware obfuscation hardens the RE process without changing its functionality, thus hindering the attacker's effort. However, none of the existing hardware obfuscation techniques protect HAs. This paper proposes a robust hardware obfuscation technique for HAs to enhance the RE complexity. It is an in-synthesis process where obfuscation is performed by inserting key-controlled blocks during architectural synthesis. The proposed obfuscation is achieved in three different ways, i.e., by obscuring the primary inputs, inserting the dummy operations, and obscuring the intermediate sub-functions. Unlike state-of-the-art methodologies, the obfuscation points are decided through a novel algorithm. We have analyzed the feasibility of the proposed approach on six different HAs for three different key sizes. Moreover, it achieves enhanced security (~12 times) with lesser design cost (~10.8%) compared to one closely related approach.