REVBiT: REVerse Engineering of BiTstream for LUT Extraction & Logic Identification

REVBiT: REVerse Engineering of BiTstream for LUT Extraction & Logic Identification

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연구 분야: Analysis

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학회: 2024 IEEE International Symposium on Circuits and Systems (ISCAS)

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초록

Field-Programmable Gate Arrays (FPGAs) are widely used in various applications due to their flexibility and reconfigurability, and they store the functionality of digital design in the form of configuration frames within the bitstream. In the earlier studies, state-of-art methodologies, such as BIL and RapidSmith reverse engineer the bitstream to identify the boolean logic of LUTs using the Xilinx ISE tool, which provides bitstream and textual information of placed design in the form of a Xilinx Design Language (XDL) file. However, the more recent tool, Xilinx Vivado, does not include XDL support or text-based hardware adjustments. To resolve the above problem, here we introduce a methodology called REVBiT for LUT extraction and boolean logic identification that offers the potential to verify functionality against a trusted reference or rectify corrupted bitstream data by correcting it. Also, our propose methodology verified on AMD Xilinx 7-Series, Ultrascale and Ultrascale+ device families FPGAs using the Xilinx Vivado tool and does not rely on additional information besides the bitstream. We achieved 100% accuracy for the LUT extraction and 93.86%, 96.26%, and 95.16% accuracy for the boolean function identification for 7-Series, Ultrascale and Ultrascale+ device families, respectively.

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