A self-certifying FPGA based pixel readout chip test system for CMS ETL detector upgrade

A self-certifying FPGA based pixel readout chip test system for CMS ETL detector upgrade

연구 분야: Databases

학회: 2023 IEEE Nuclear Science Symposium, Medical Imaging Conference and International Symposium on Room-Temperature Semiconductor Detectors (NSS MIC RTSD)

This talk presents a flexible self-certifying FPGA-based pixel readout test system for testing the Endcap Timing Read-Out Chip (ETROC) being developed for the CMS MIP Timing Detector (MTD). The system includes an FPGA-based emulator and a test system. The test system can take data from emulator or up to four ETROC test boards in beam telescope mode and is compatible with both ETROC1 and ETROC2 boards. A python-based GUI simplifies configuration and calibration. The system provides an efficient and reliable solution for testing ETROC chips and can be extended to other readout chips with similar architecture.