Accelerating Automated Driving and ADAS Using HW/SW Codesign

Accelerating Automated Driving and ADAS Using HW/SW Codesign

연구 분야: Verification

학회: 2024 IEEE 37th International System-on-Chip Conference (SOCC)

With the growing demands of increasing levels of automation in driving capabilities, AI workloads are being increasingly deployed. However, AI-based solutions are compute-intensive. Hence, to achieve market readiness, practical automated driving solutions need to deliver adequate efficiency, measured as compute performance (TOPS/s) per given power budget. For example - the above ratio directly impacts the range of electric vehicles (EVs) and plays a crucial role in deciding the foreseeable future of the automotive sector. Emerging technology such as in-memory computing can be a viable enabler to achieve this next level of AI acceleration to pave the route towards actual product realizations. In-memory computing is a disruptive technology that shifts the computing paradigm from classical digital computing with frequent data transfers into the analog and static data domain of up to 1000 TOPS/s. However, to truly tap the potential of in-memory computing, it requires an efficient integration into the HW/SW stack. This paper presents a holistic HW/SW-codesign approach covering the entire stack from neural architecture search (NAS) to generate efficient networks, optimization of the network involving compression techniques, exploring deployment strategies on the HW, along with discussion related to functional safety. It has been demonstrated that with joint optimization, we reach {1 5 0 \%} improvement in FPS (frames-per-second) over the baseline.