SIZALIZER: Multilevel Analysis Framework for Object Size Optimization

SIZALIZER: Multilevel Analysis Framework for Object Size Optimization

연구 분야: Verification

학회: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Due to the resource constraints and the increasing environmental impact of embedded systems, the development of frameworks to optimize the footprint of instruction set architectures becomes critical. This paper presents SIZALIZER, a multi-layer analysis framework for the co-design of embedded C/C++ applications and RISC-V instruction set extensions. SIZALIZER embodies a novel approach by automating analysis across three layers: LLVM intermediate representation, executable binary code, and runtime instruction execution using techniques such as data flow graph, static binary, and dynamic execution analysis. The analysis performed with the Embench benchmark demonstrates SIZALIZER’s potential to identify optimization opportunities for both static and dynamic code sizes. The framework’s unique architecture enables it to distill actionable insights from complex software structures and guide size-optimizing ISA improvements. The proposed improvements result in a calculated static and dynamic improvement of approximately 30 %.