Security of Hardware Generators: Enabling Assurance in High-Level Synthesis

Security of Hardware Generators: Enabling Assurance in High-Level Synthesis

연구 분야: Verification

학회: 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)

The ever-increasing usage of high-level-synthesis (HLS), particularly in AI and crypto applications, for mitigating aggressive demand for microelectronics, led to advanced optimization of backend infrastructures, i.e., allocation, scheduling, and binding of HLS tools in terms of power, performance, and area. However, in safety-critical applications utilizing AI/crypto cores, hardware generator automation flows must also be secure and trustworthy, from the design phase to the end-user application. In this paper, we propose three different solutions on what we can offer to address such a shortcoming in HLS flow and how security awareness could be added to it in an automatic manner: (1) PRAGMAs but for security via tool vendors; (2) analysis and re-touching the intermediate representation (IRs) for security properties; (3) enabling security-awareness in HLS backend steps, focusing on scheduling and binding. We represent a case study per each solution, and by demonstrating the details of each solution, we compare the efficacy of such solutions w.r.t. the security as well as power“performance” and area overhead.