Software-defined Temporal Decoupling in Virtual Platforms

Software-defined Temporal Decoupling in Virtual Platforms

연구 분야: Verification

학회: 2021 IEEE 34th International System-on-Chip Conference (SOCC)

As developers struggle with the ever rising complexity of HW/SW systems, the demand for high-performance full system simulators increases. So called virtual platforms, built using SystemC TLM 2.0, have tried to fill that need for early software verification and HW/SW co-design. Unfortunately, the increasing system complexity has not left the simulator’s performance untouched. As they are sequential, adding more simulation components slows simulation execution. Temporal decoupling was introduced to satisfy the requirement of ever higher simulation speed by sacrificing some simulation accuracy. This is implemented by allowing simulation components to run ahead of the global simulation time by a static, predefined amount of time called quantum. The standardized SystemC TLM 2.0 static quantum approach however, does not lead to general performance improvements in all scenarios. One of the main reasons for this is, that the requirements towards the temporal decoupling strategy change over the simulation’s duration and depend strongly on the executed target software. Therefore, a novel adaptive temporal decoupling technique is proposed in this work, that takes these requirements into account. This is achieved by non-invasive runtime profiling of the simulation and a later optimization of the temporal decoupling strategy using the gathered information. As shown in the case study of this work, the technique allows for performance increases of up to 5.87x compared to SystemC’s static quantum approach in the presented benchmarks.