Accelerating GLS Simulation closure in DFT with Emulator

Accelerating GLS Simulation closure in DFT with Emulator

연구 분야: Verification

학회: 2021 IEEE International Test Conference India (ITC India)

To keep pace with the demands of advanced complex SoC development and to close the HW /SW verification gap, Emulation is increasingly used as a scalable and reusable solution. As part of a quicker execution schedule, DFT Engineers deploy optimum methods of RTL, ATPG, MBIST verification, and even proto-type complete RTL into Emulator for faster RTL verification closure. Another integral part of DFT verification is Gate-Level Simulation of MBIST and ATPG patterns but done in small volume due to huge simulator-time requirement leading to incomplete closure. We propose vector-mode based Gate level emulation (GLE) for DFT patterns. This paper talks about 500-to-1500X performance gain when simulating MBIST and ATPG complete pattern set in Emulator over GLS. Results show that for 2 SOCs of size 36M, 55M gates, a complete stuck-at, and transition ATPG WGL format pattern set of 90k can be simulated in Emulator within hours. Manufacturing Algorithm-based MBIST WGL patterns which take weeks in the EDA simulator can be emulated in minutes. This provides closure of DFT Pre-silicon GLS Verification within a day. The verified WGL patterns can be seamlessly ported to ATE Tester program for post-silicon Bring-up, bridging the verification gap between RTL and silicon device. The paper also shows a method of debugging ATPG and MBIST pattern failures with debug logs and waveforms dumped from the Emulator program.