HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction Model

HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction Model

연구 분야: Verification

학회: 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

In recent years, Rust has emerged as a powerful programming language, offering significant advantages over traditional design languages such as C and \mathrm{C}++ . Rust’s features, including memory safety, concurrency without data races, and a strong type system, make it uniquely suited for developing reliable and efficient embedded systems. Despite these benefits, formal hardware-software co-verification methods have not kept pace with the advancements in Rust. Current co-verification approaches often struggle with complexity and insufficient integration between hardware and software components, leading to incomplete verification processes and potential undetected bugs. To address these challenges, we propose a novel approach by constructing a Rust-based hardware abstraction model that seamlessly integrates both hardware and software verification. This model leverages Rust’s inherent safety features to facilitate a more robust co-verification process. Additionally, we have developed a comprehensive hardware-software co-verification framework that can be deployed throughout the entire development life cycle, from initial design to final deployment. This framework ensures continuous and thorough verification, significantly reducing the likelihood of undetected bugs. We applied our proposed framework to several industrial and open-source designs, demonstrating its effectiveness in identifying multiple bugs in a significantly reduced time frame. The results highlight the efficiency and reliability of our Rust-based hardware-software co-verification framework, paving the way for more secure and robust system designs in the future.