Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design

Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design

연구 분야: Verification

학회: ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Processing-in-memory (PIM) based architecture shows great potential to process several emerging artificial intelligence workloads, including vision and language models. Cross-layer optimizations could bridge the gap between computing density and the available resources by reducing the computation and memory cost of the model and improving the model's robustness against non-ideal hardware effects. We first introduce several hardware-aware training methods to improve the model robustness to the PIM device's non-ideal effects, including stuck-at-fault, process variation, and thermal noise. Then, we further demonstrate a software/hardware (SW/HW) co-design methodology to efficiently process the state-of-the-art attention-based model on PIM-based architecture by performing sparsity exploration for the attention-based model and circuit-architecture co-design to support the sparse processing.