LLM-Sec: Closing the Security Loop using LLMs for Hardware Design

LLM-Sec: Closing the Security Loop using LLMs for Hardware Design

연구 분야: Verification

학회: 2025 IEEE International Conference on Omni-layer Intelligent Systems (COINS)

The term "closing the loop" effectively captures the concept of creating a complete, automated security cycle that addresses the current gap between security threat identification and mitigation in hardware design. Current research shows that hardware security verification processes are predominantly manual, labor-intensive, and struggle to scale with increasing design complexity. This work aims to address this challenge by envisioning LLMs to automate both the detection and resolution phases, creating a true closed-loop system for secure hardware design. While providing a survey of LLM-driven hardware security frameworks, this work aims to highlight the critical concept of security loop closure leveraging the power of LLMs and security feedback to drive security closure of hardware designs. The framework outlines the techniques to incorporate comprehensive feedback mechanisms for quality assurance, including automated evaluation metrics, human expert validation, and cross-verification with multiple LLM agents to ensure reliability and accuracy of security assessments.