CAD Tools Pathway in Hardware Security

CAD Tools Pathway in Hardware Security

연구 분야: Verification

학회: 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)

In modern computer devices, System-on-Chip (SoC) technology is used to design hardware components. The most sensitive assets of a SoC design are the encryption key, configuration settings, and data stored on the device. As the semiconductor industry has become more globalized, there is an increased risk of unauthorized access to SoC assets in light of the outsourcing of the design process and the integration of third-party intellectual property (3PIP). There are significant security concerns when using 3PIP from different vendors since any threats may be inserted into the SoC design by an attacker. The designer must add IP countermeasures to the SoC to protect it from design flow vulnerabilities. To ensure the security and trustworthiness of IPs and SoC designs, they must be validated as security assets. Security issues in modern designs have become more challenging due to their complexity, and existing tools cannot resolve them. Security concerns may not be considered when designing tools optimized for area, power, and performance. To address security issues in the SoC design process, computer-aided design (CAD) tools and techniques are being developed to assess potential threats and detect security vulnerabilities. By addressing each vulnerability in the SoC design flow, these CAD tools automate security assessments as well as validate preferred metrics. In this paper, we explore the state-of-the-art of CAD tools usage in hardware security verification and validation. Here, we present the systematic utilization of CAD tools in the SoC design lifecycle, including their strengths and weaknesses. Finally, the paper concludes with an assessment of where we are with current research and directions for future research.