Web-Based Simulator of Superscalar RISC-V Processors


연구 분야: Verification



학회: SC-W '24: Proceedings of the SC '24 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis


초록

Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills.


Author Profile
Jiří Jaroš

Brno University of Technology Brno Czech Republic

Czech Republic
Author Profile
Michal Majer

Brno University of Technology Brno Czech Republic

Czech Republic
Author Profile
Jakub Horky

Brno University of Technology Brno Czech Republic

Czech Republic

📄 논문 정보

발행 연도 2025년
인용수 0
출판 국가 Czech Republic
사이트 ACM
좋아요 수 0

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