FPGA Software Security Testing Excitation Random Generation Based on SFMEA and SFTA

FPGA Software Security Testing Excitation Random Generation Based on SFMEA and SFTA

연구 분야: Verification

학회: 2019 6th International Conference on Dependable Systems and Their Applications (DSA)

According to the analysis and research of SFMEA and SFTA technology, this paper provides an FPGA software security test excitation random generation technology based on SFMEA and SFTA reverse synthesis. Firstly, establish the FPGA software fault tree through SFTA. Secondly, the SFMEA is performed for the important bottom event, analyze the potential fault effect and supplement the fault tree. Then refine the test constraints according to the bottom event. Finally generate the security random test stimulus using the verification language. This technology can effectively improve the sufficiency of FPGA software security testing, standardize the testing process, and ultimately improve software security and ensure software quality.