Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue

Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue

연구 분야: Verification

학회: DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference

Most Register Transfer Level (RTL) designs originate from behavioral descriptions specified in C or C++ often written by Software (SW) designers. Hardware (HW) designers then manually describe an efficient hardware implementation of that application using a Hardware Description Language (HDL) like Verilog or VHDL. Although it has been shown that High-Level Synthesis (HLS) provides a direct path to synthesizing these behavioral descriptions into RTL, the quality of the generated RTL is often still unacceptable, hence, requiring to manually design the HW. This is nevertheless time consuming and error prone. In particular, finding bugs introduced in the manual design is very tedious as HW designers rely on long simulations that generate large waveforms that have to be thoroughly scrutinized. To address this, in this work we present an automated method to accurately point to where in an RTL description a bug is located by using HLS. In particular we leverage the ability of HLS to generate a variety of different micro-architectures to automatically find a design architecturally 'similar' to the manually optimized one in order to help locate the bugs. This also involves automatically updating the HLS technology library in order to match the delay from floating-point functional units (FUs) such that these match the equivalent integer functional units used in the manually optimized RTL design as one of the main optimization that can lead to numerical stability issues in the manual translation is floating-point to fixed-point data translation.