Error Detecting and Correcting Codes for DRAM Functional Safety

Error Detecting and Correcting Codes for DRAM Functional Safety

연구 분야: Verification

학회: MEMSYS '23: Proceedings of the International Symposium on Memory Systems

With the evolution of Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) in vehicles, processing requirements in Electronic Control Units (ECUs) increase significantly. Traditional microcontrollers using embedded flash and/or embedded SRAM to store data and execute program code are not performant enough. These automotive microcontrollers have for a long time been optimized for best quality and highest safety standards. New architectures with high performance multi-core System-on-Chip (SoC) designs and significant external DRAM need to follow the same path to assure functional safety. In this paper, we first provide an overview over failure modes of DRAM devices. After this we’ll analyze the behavior of common Error Correcting (ECC) and Error Detecting (EDC) Codes with the respect to their coverage of DRAM failure modes. We will show that simple Single-Bit Correcting Double-Bit Detecting (SEC-DED) ECC codes do not provide sufficient Diagnostic Coverage (DC) for multi-bit (MBE) and addressing errors that occur in DRAM devices with significantly high FIT (Failure-In-Time) rates. The properties of popular ECC and EDC codes for their MBE DC will be derived analytically and in addition verified through simulations. Coding schemes with sufficient DC to build functionally safe DRAM sub-systems will be proposed. We will finally provide a generic equation to calculate MBE DC for any linear block code including CRC, Hamming, Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon (RS) codes.