Hybrid AXI Bus Interconnect Structure Design for FPGA-Based Image Processing Systems

Hybrid AXI Bus Interconnect Structure Design for FPGA-Based Image Processing Systems

연구 분야: Infrastructure

학회: AIPR '24: Proceedings of the 2024 7th International Conference on Artificial Intelligence and Pattern Recognition

In the digital era, image processing technology is crucial for key areas such as security monitoring, medical imaging, and intelligent transport. FPGA-based image processing systems have become the first choice for design due to their high parallel computing capability and programmability. However, existing FPGA-based image processing systems often need to compromise on system area and complexity to pursue high real-time and high performance. To this end, this paper proposes a hybrid interconnect architecture that incorporates ShareBus and Crossbar based on the AXI bus. The architecture assigns IP modules to the corresponding sub-interconnect modules according to the speed of the data transfer rate and introduces an arbitration module with weights and a caching mechanism with random access queues. The experimental results demonstrate that the two interconnect submodules, ShareBus and Crossbar, improve the performance by 14.7% and 5.5%, respectively, compared with calling IP, which overall improves the data transmission capability and reduces the complexity, achieves efficient management and scheduling, and provides a new way of thinking for optimizing the performance of the image processing system.