Homomorphic Encryption and Decryption Hardware Design using Shared Arithmetic and Configurable Butterfly Unit

Homomorphic Encryption and Decryption Hardware Design using Shared Arithmetic and Configurable Butterfly Unit

연구 분야: Cryptography

학회: 2025 International Conference on Electronics, Information, and Communication (ICEIC)

With the widespread adoption of cloud computing, ensuring data privacy and security has become a critical challenge. In this context, homomorphic encryption has gained significant attention due to its unique ability to perform computations on encrypted data. This paper proposes an area-efficient and low-complexity hardware design for LWE-based homomorphic encryption systems. The proposed design integrates NTT/INTT/ModMult operations into a single configurable but-terfly unit, reducing hardware complexity. Our design achieves approximately 23% fewer clock cycles than traditional NTT hardware architectures. Compared to previous works, our design achieves 3.7\times and 2.8\times better efficiency. Hardware resource optimization is achieved using a unified butterfly architecture and a shared arithmetic in the encryption/decryption process.