Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization

Design and Analysis of Low Power Reversible Majority Logic-Based Adder/Subtractor Circuits with Parallel Computing Optimization

연구 분야: Cryptography

학회: SN Computer Science

The increasing circuit density in CMOS technology is often accompanied by rising power consumption, posing significant challenges in modern Very Large Scale Integration (VLSI) designs. As device dimensions continue to shrink, power dissipation and heat generation become major constraints, necessitating the development of alternative computing paradigms. One promising solution is Reversible Logic Gate-based Implementation, which preserves information and minimizes energy loss. Another approach, Majority Logic in Approximate Computation Designs, reduces power by using fewer logic gates, ideal for error-tolerant applications. This work proposes a Quantum Majority Gate-Based Adder/Subtractor that integrates reversible logic with majority-based computation to achieve lower quantum cost, reduced garbage outputs, and improved scalability. Additionally, the design incorporates parallel computing optimization techniques, enabling high-speed arithmetic operations with reduced latency. Performance evaluations validate the architecture’s superiority over traditional reversible logic circuits, demonstrating significant improvements in power efficiency and computational throughput. By leveraging quantum-inspired reversible gates and parallelism, this design lays a foundation for next-generation low-power, scalable circuits suitable for quantum computing, nanotechnology, and energy-constrained environments.