High Throughput VLSI Architecture for Bilateral Filtering in Computer Vision

High Throughput VLSI Architecture for Bilateral Filtering in Computer Vision

연구 분야: Artificial Intelligence

학회: 2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)

Bilateral (BL) filtering is becoming de-facto noise filtering for computer vision and analytics processing systems due to its edge-preserving property. The prior literature address - Bilateral filtering by its direct implementation, which has higher computational complexity and is restricted to non-embedded applications. This paper proposes a novel solution to Bilateral filtering with significant complexity reduction enabling 720 MPixel/second throughput hardware IP in 16nm FinFET. The paper proposes multiple novelties namely Space and amplitude quantized Fixed point 2D-LUT, mixed-mode 1D Division LUT, and an efficient content-adaptive algorithm for Bilateral Filtering. Additionally, the given solution is flexible to support Octave scaling for image pyramid generation and generic 2D convolution engine in computer vision applications. The proposed solution requires 1/80 amount of 2D LUT compared to direct implantation. The image quality results show negligible pixel deviation in noise filtering output with a range of 1-3-pixel rms compared to pc based floating reference.