Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited)

Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited)

연구 분야: Cryptography

학회: 2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. A variety of physical attacks may compromise the security of cryptographic operations. Electromagnetic (EM) and power current traces of an IC chip deliver secret information to some extent, as known as side-channel (SC) leakage, since they are strongly correlated with internal toggling among digital logic cells. The EM and laser irradiation intentionally induce bit-level faults, which may effectively reduce the search space of secret information. Advanced packaging techniques, including 2.5D IC chip packaging and 3D IC chip stacking, provide the opportunity to gain the higher level of protection against physical attempts by an adversary. The Si substrate of any IC chip can become the easiest attack surface, however, which is prevented by exploiting backside buried metal (BBM) wirings. The Si BBM and 3D chip stack structures have been combined for IC chip performance and SC leakage mitigation. We will discuss measurements and analysis on fabricated demonstrators of cryptographic functionality, where the capacitances at intertier interfaces and shields on the topmost tier exhibit prominent effects against SC leakages.