연구 분야: Cryptography
학회: 2025 5th International Conference on Neural Networks, Information and Communication Engineering (NNICE)
As the security and trust root of cryptography chips, the Physical Unclonable Function (PUF) is widely used in information security fields such as key management, secure boot, and device authentication of cryptographic chips, re-configurable network security processors. Recently, the researchers from the domestic and foreign have proposed a variety of PUF circuit structures and validated on Field Programmable Gate Arrays (FPGAs). However, most of the current verification platforms are based on single-chip FPGAs, which cannot meet the functional and performance testing requirements for the implementation of multiple batches of PUFs in the same batch. In addition, the existing validation platform cannot meet the requirement of large-scale, automated, real-time, and dynamic PUF testing. Therefore, this paper designs a customized hardware testing circuit based on FPGAs, proposes a PUF testing architecture with communication interfaces, error correction, and security enhancement module, builds a hardware testing platform, and develops a software tool for automatic response collection and performance analysis based on LabView. This system realizes the automatic sending of stimuli, real-time collection of responses, and online analysis of performance, providing platform support and technical support for the design verification of PUFs, thereby enhancing the security of reconfigurable network cryptographic processors. Furthermore, the arbiter PUF is taken as the test object for verification in this paper. The PUF circuits are implemented on 36 FPGAs, and a large number of stimulus-response pairs are collected. The stability and randomness of the PUF are all close to the ideal values.
| 발행 연도 | 2025년 |
|---|---|
| 인용수 | 13 |
| 출판 국가 | Andorra |
| 사이트 | IEEE |
| 좋아요 수 | 0 |