High-speed SABER key encapsulation mechanism in 65nm CMOS

High-speed SABER key encapsulation mechanism in 65nm CMOS

연구 분야: Cryptography

학회: Journal of Cryptographic Engineering

Quantum computers will break cryptographic primitives that are based on integer factorization and discrete logarithm problems. SABER is a key agreement scheme based on the Learning With Rounding problem that is quantum-safe, i.e., resistant to quantum computer attacks. This article presents a high-speed silicon implementation of SABER in a 65nm technology as an Application Specific Integrated Circuit. The chip measures 1 in size and can operate at a maximum frequency of 715 at a nominal supply voltage of 1.2V. Our chip takes 10, 9.9 and 13 μ for the computation of key generation, encapsulation, and decapsulation operations of SABER. The average power consumption of the chip is 153.6 . Physical measurements reveal that our design is 8.96x (for key generation), 11.80x (for encapsulation), and 11.23x (for decapsulation) faster than the best known silicon-proven SABER implementation.