Implementing a Secure Boot System on a 32-Bit RISC-V CPU on FPGA

Implementing a Secure Boot System on a 32-Bit RISC-V CPU on FPGA

연구 분야: Cryptography

학회: 2024 RIVF International Conference on Computing and Communication Technologies (RIVF)

This work presents an implementation of system-on-chip (SoC), integrating a secure boot procedure based on a 32-bit RISC-V architecture CPU and hardware-accelerated cryptographic cores on an FPGA. The implementation utilized an open-source framework to build and integrate the system, which included the 32-bit VexRiscv CPU core designed in SpinalHDL, cryptographic cores of Poly1305, ChaCha, and SHA3-512 designed in Verilog HDL to ensure the security of the system as well as the firmware versions used in the secure boot process. Large files could be hashed using the Tree Hash algorithm. The system was then successfully deployed on the FPGA development board Arty A7-100T. Software was also developed to verify the functionality of the SoC system with the integrated cryptographic cores during the secure boot process.