FPGA Based Accelerator for Image Steganography

FPGA Based Accelerator for Image Steganography

연구 분야: Strategies

학회: Asia Simulation Conference

In this study, a novel approach is proposed for enhancing the speed and efficiency of steganography system by designing a hardware model that adopts the image-in-image (grey-in-color) method and utilizes the Least Significant Bit (LSB) algorithm. The sizes of secret and cover images are chosen so that all secret bits can be embedded inside the LSB bits of the pixels for the three RBG matrices for the cover image and produce the color stego-image. On the receiving part, these embedded secret bits will be extracted from stego-image and reform the original secret image. Using XSG and Vivado design suite, a successful FPGA-based steganography system was developed as an accelerator tool with high-speed processing that reaches 250 times faster than the software-based system. The quality of the stego-image and the extracted secret image was calculated by three metrics, which are the Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), and Cross Correlation (CCR). The comparison metrics values affirm a high level of trust in the generated stego-image, and the extracted secret image being identical to the original. The FPGA chip utilized in the implemented system consumes only 1% of the hardware resources, and a remarkable speedup factor of 250 is achieved, indicating that expanding the system for larger image sizes becomes highly feasible. Moreover, this expansion can be accomplished economically by utilizing low-cost field-programmable gate array (FPGA) chips.