Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

연구 분야: Networking

학회: Artificial Life and Robotics

The verification of image processing hardware using FPGAs requires various peripherals. Although commercially available FPGA boards also include peripherals, it is necessary to design and implement interface circuits to use them. Furthermore, since each board has different peripherals, new interfaces have to be designed each time. Also, these interface circuits are not generated by HLS. Therefore, we are developing a hardware verification environment that is independent of the peripherals of FPGA boards. The verification environment we proposed last time consists of a general-purpose FPGA board, a PC, and server/client programs running on the PC and on the CPU of the FPGA board. By virtualizing the peripherals to be installed in the product on the PC, verification can be performed regardless of the peripherals on the FPGA board. TCP/IP communication also makes it possible to verify huge images. However, in this verification environment, each verification has to be compiled on the FPGA implementation tool. Therefore, in this paper, we aim to create a verification environment in which hardware can be replaced dynamically during verification by implementing DPR.