100G Ethernet Data Application and Slicing Design and Implementation

100G Ethernet Data Application and Slicing Design and Implementation

연구 분야: Networking

학회: 2024 6th International Conference on Frontier Technologies of Information and Computer (ICFTIC)

With the rapid development of technologies such as cloud computing, big data, and the Internet of Things, the bandwidth and delay of Ethernet data transmission have become the key factors limiting performance. In order to deal with the problems of processor resource overload and network delay caused by network protocol processing in the transmission of large amounts of Ethernet[1], this paper proposes a design method for 100G Ethernet data application and slicing strategy, which realizes the multi-queue data application mechanism through interaction with QDMA based on descriptors, and at the same time, designs a large block fragmentation transmission mechanism, adopts a pipeline architecture, and supports TCP/IP packet checksum offloading function. It effectively reduces the delay of sending large data blocks and the occupation of processor resources [2]. Experimental results show that the design scheme of 100G Ethernet data application and slicing designed in this paper can efficiently process the network communication protocol in the high-concurrency network communication scenario, and the network communication bandwidth remains relatively stable, with a large packet transmission rate of 36Gbps and an average delay of 180 microseconds.