Enhancing SRAM Array Security Through Transmission Gate-Based Logic Obfuscation

Enhancing SRAM Array Security Through Transmission Gate-Based Logic Obfuscation

연구 분야: Analysis

학회: 2024 IEEE 33rd Asian Test Symposium (ATS)

Logic obfuscation is a crucial technique in hardware security aimed at shielding integrated circuits (ICs) from threats such as reverse engineering and intellectual property theft. This research introduces an innovative approach by incorporating transmission gates into logic obfuscation mechanisms to bolster security within SRAM arrays. We propose and implement a distinctive locking mechanism utilizing transmission gates, applied to the word lines of a 4x4 SRAM array. This mechanism effectively regulates access to the memory cells, ensuring that data can only be read or written with the correct key input. To assess the efficacy of our approach, we evaluate the transistor count, power consumption, write access time, and read access time of the obfuscated SRAM array in comparison to a conventional, non-obfuscated SRAM array. Our experimental results reveal that, although the locking mechanism leads to a slight increase in power consumption, write access time, and read access time, these changes are minimal and within the range of typical circuit variations. The proposed method significantly enhances SRAM array security with only a marginal impact on performance, demonstrating its potential for safeguarding sensitive data in digital systems