FPGA-based Realization of Processor Unit with Key-Based Logical Obfuscation

FPGA-based Realization of Processor Unit with Key-Based Logical Obfuscation

연구 분야: Analysis

학회: 2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)

Conventionally, Integrated Circuit (IC) design is done without any concern for hardware security and hence IC design is vulnerable to reverse engineering (RE), piracy, and overbuilding. Hardware security aims to prevent piracy and RE by obfuscating and camouflaging. The main aim of the work is to design an obfuscated 16-bit instruction set architecture (ISA) of an Instructional Processor unit that has the capabilities to perform arithmetic and logical operations, with a predefined set of instructions and investigate the overhead in terms of area and power caused by practical logic obfuscation. Parts of the data path and the control path are obfuscated using key-based multiplexers, to provide hardware security. Through obfuscation, unique physical structures like logic gates are added to ICs in such a way that only the designer of the circuit can enable and disable correct functional execution, and this makes it difficult to deduce during reverse engineering. Key-based obfuscation has the advantage of being a stronger obfuscation method in terms of increasing the time complexity of deciphering the correct key even with shorter keys. Thus, this method was chosen to secure the designed processor’s data path and the control path at the fundamental sub-circuit level, thus having a greater influence on the output. The Processor unit is modeled using Verilog Hardware De- scription Language (HDL) in Xilinx Vivado 2015.3 and synthesized and implemented in the Zedboard-Zynq 7000 (XC7Z020-CLG484 -1). Experimental results demonstrate the comparison of resources utilized (area), timing, and power for an obfuscated and non-obfuscated design to investigate the overhead.