Exploiting Static Power Consumption in Side-Channel Analysis

Exploiting Static Power Consumption in Side-Channel Analysis

연구 분야: Analysis

학회: 2024 IEEE 25th Latin American Test Symposium (LATS)

Nowadays, CMOS is the dominant technology for integrated circuits fabrication due to its low power consumption and scalability. Power consumption in CMOS devices consists of dynamic and static components, with dynamic power arising from transistor switching and static power from current leakage. The power consumption of a device implementing cryptographic operations may be exploited to reveal secret information processed by the device. Such kinds of attacks are known as Side-Channel Analysis (SCA) attacks. While SCA attacks analysing dynamic power are widely studied, static power analysis poses new challenges in hardware security due to its increasing impact on the overall power consumption with technology scaling. There are a few studies only that have addressed static power as a side-channel leakage for cryptographic key extraction. Very recent research shows success in attacking symmetric block ciphers. This paper is the work describing exploitation of static power in attacking asymmetric cryptographic approaches, particularly targeting the kP operation. By analysing the current leakage trace, we were able to reveal a significant part of the applied cryptographic key.