DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security

DPReDO: Dynamic Partial Reconfiguration enabled Design Obfuscation for FPGA Security

연구 분야: Analysis

학회: 2022 IEEE 35th International System-on-Chip Conference (SOCC)

FPGA security is being challenged by reverse engineering, Trojan, and side-channel analysis attacks. Although the existing static obfuscation methods can protect the integrated circuits from IP piracy and hardware tampering, they are still vulnerable to persistent attacks in FPGAs. In this work, we leverage the advanced function of FPGA CAD tools to develop a Dynamic Partial Reconfiguration enabled Design Obfuscation (DPReDO) method. FPGA emulation results show that, for each obfuscation variant update, the proposed dynamic obfuscation method only consumes 1.5% of the FPGA reconfiguration time required by an existing static obfuscation. Our case study shows that the netlist synthesis time of our method is 26% less than the baseline.