Innovation Practices Track: Security in Test and Test for Security

Innovation Practices Track: Security in Test and Test for Security

연구 분야: Analysis

학회: 2022 IEEE 40th VLSI Test Symposium (VTS)

VLSI testing is essential to guarantee the correct functionality of the chip design. The recent advances in hardware security have posed new challenges for testing. In this IP session, we discuss the security in test and test for security through three talks. First, we give a brief overview of the security vulnerabilities and countermeasures in scan chain design, followed by a detailed discussion of a new configurable partial scan design approach. Second, we present the challenges in testing the security of design at various design stages and propose a strategy to identify potential security vulnerabilities in early design stages. Finally, we consider physical unclonable function (PUF) and develop an adaptive framework based on machine learning for the test and error correction of PUF designs.