PARS: A Layered Hardware Obfuscation Platform for Resilience and Secure Collaborative Multi-Module Designs

PARS: A Layered Hardware Obfuscation Platform for Resilience and Secure Collaborative Multi-Module Designs

연구 분야: Analysis

학회: ACM SIGCOMM Posters and Demos '25: Proceedings of the ACM SIGCOMM 2025 Posters and Demos

As hardware design becomes outsourced, protecting intellectual property (IP) from reverse engineering and counterfeiting is a challenge. Logic locking provide a promising solution, but existing approaches fail to balance security, performance, and scalability. We present PARS, a scalable obfuscation platform that integrates locking techniques tailored to different hardware granularity: standalone IPs, multi-module, and Network-on-Chip (NoC) communications. PARS balances overhead and security (ranging from standalone to multi-module systems and networked architectures) to defeat SAT-based, approximate, and learning-based deobfuscation attacks and is a well-suited solution for large designs.