정의: SystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic systems in the semiconductor and electronic design industry. SystemVerilog is an extension of Verilog.
| 핵심 연구 분야 | Verification |
|---|---|
| 주요 연도 | 2022년 |
| 주요 연관 키워드 | engineering |
| 좋아요 수 | 0 |